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l4972a L4972AD june 2000 2a switching regulator ? . 2a output current . 5.1v to 40v output voltage range . 0 to 90% duty cycle range . internal feed-forward line reg. . internal current limiting . precise 5.1v 2% on chip reference . reset and power fail functions . input/output sync pin . under voltage lock out with hys- teretic turn-on . pwm latch for single pulse per pe- riod . very high efficiency . switching frequency up to 200khz . thermal shutdown . continuous mode operation description the l4972aisa stepdownmonolithicpower switch- ing regulatordelivering 2a at a voltagevariable from 5.1 to 40v. realized with bcd mixed technology, the device uses a dmos output transistor to obtain very high efficiency and very fast switching times. features of block diagram powerdip (16 + 2 + 2) the l4972a include reset and power fail for micro- processors, feed forward line regulation, soft start, limiting current and thermal protection. the device is mountedin a powerdip16 + 2 + 2 and so20 large plastic packages and requires few external compo- nents. efficient operation at switching frequencies up to 200khz allows reduction in the size and cost of external filter component. ordering numbers : l4972a (powerdip) L4972AD (so20) 1/23 this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. so20 multipower bcd technology
pin connection (top view) thermal data symbol parameter powerdip so-20 r th j-pins r th j-amb thermal resistance junction-pins max thermal resistance junction-ambient max 12 c/w 60 c/w 16 c/w 80 c/w absolute maximum ratings symbol parameter value unit v 11 input voltage 55 v v 11 input operating voltage 50 v v 20 output dc voltage output peak voltage at t = 0.1 m s f = 200khz -1 -5 v v i 20 maximum output current internally limited v i boostrap voltage boostrap operating voltage 65 v 11 +15 v v v 4 ,v 8 input voltage at pins 4, 12 12 v v 3 reset output voltage 50 v i 3 reset output sink current 50 ma v 2 ,v 7 ,v 9 ,v 10 input voltage at pin 2, 7, 9, 10 7 v i 2 reset delay sink current 30 ma i 7 error amplifier output sink current 1 a i 8 soft start sink current 30 ma p tot total power dissipation at t pins 90 c at t amb =70 c (no copper area on pcb) 5 / 3.75(*) 1.3/1 (*) w w t j ,t stg junction and storage temperature -40 to 150 c (*) so-20 l4972a-L4972AD 2/23
pin functions n o name function 1 bootstrap a c boot capacitor connected between this terminal and the output allows to drive properly the internal d-mos transistor. 2 reset delay a c d capacitor connected between this terminal and ground determines the reset signal delay time. 3 reset out open collector reset/power fail signal output. this output is high when the supply and the output voltages are safe. 4 reset input input of power fail circuit. the threshold is 5.1v. it may be connected via a divider to the input for power fail function. it mustbe connected to the pin 14 an external 30k w resistor when power fail signal not required. 5, 6 15, 16 ground common ground terminal 7 frequency compensation a series rc network connected between this terminal and ground determines the regulation loop gain characteristics. 8 soft start soft start time constant. a capacitor is connected between thi sterminal and ground to define the soft start time constant. 9 feedback input the feedback terminal of the regulation loop. the output is connected directly to this terminal for 5.1v operation; it is connected via a divider for higher voltages. 10 sync input multiple l4972a's are synchronized by connecting pin 10 inputs together or via an external syncr. pulse. 11 supply voltage unregulated input voltage. 12, 19 n.c. not connected. 13 v ref 5.1v v ref device reference voltage. 14 v start internal start-up circuit to drive the power stage. 17 oscillator r osc . external resistor connected to ground determines the constant charging current of c osc . 18 oscillator c osc . external capacitor connected to ground determines (with r osc ) the switching frequency. 20 output regulator output. l4972a-L4972AD 3/23
the l4972a is a 2a monolithic stepdown switching regulatorworking in continuousmode realized inthe new bcd technology. this technology allows the integration of isolated vertical dmos power transis- tors plus mixed cmos/bipolar transistors. the device can deliver 2a at an output voltage ad- justable from 5.1v to 40v and contains diagnostic and control functions that make it particularly suit- able for microprocessor based systems. block diagram the block diagram shows the dmos power tran- sistors and the pwm control loop. integrated func- tions include a reference voltage trimmed to 5.1v 2%,soft start, undervoltagelockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. the reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. device turn on is around 11v with a typical 1v hys- terysis, this threshold porvides a correct voltage for the driving stage of the dmos gate and the hyste- rysis prevents instabilities. an externalbootstrapcapacitorchargeto 12v by an internal voltage reference is needed to provide cor- rect gate drive to the power dmos. the driving cir- cuit is able to source and sink peak currents of around 0.5a to the gate of the dmos transistor. a typical switching time of the current in the dmos transistor is 50ns. due to the fast commutation switching frequencies up to 200khz are possible. the pwm control loop consists of a sawtooth oscil- lator, error amplifier, comparator, latch and the out- put stage. an error signal is producedby comparing theoutputvoltagewiththe precise5.1v 2% on chip reference. this error signal is then compared with the sawtooth oscillator in order to generate frixed frequency pulse width modulated drive for the out- put stage. a pwm latch is included to eliminate multiple pulsing within a period even in noisy envi- ronments. the gain and stabilityof the loop can be adjustedby an external rc network connected to the output of the error amplifier. a voltage feedforward control has been added to the oscillator, this maintains su- perior line regulation over a wide input voltage range. closing the loop directly gives an outputvol- tage of 5.1v, higher voltages areobtained by insert- ing a voltage divider. at turn on, outputovercurrents are prevented by the soft start function (fig. 2). the error amplifier is in- itially clamped by an externalcapacitor,css, and al- lowed to rise linearly under the charge of an internal constant current source. output overload protection is provided by a current limit circuit. the load current is sensed by a internal metalresistor connectedto a comparator.when the load current exceeds a preset threshold, the output of the comparator sets a flip flop which turns off the power dmos. the next clock pulse, from an internal 40khz oscillator, will reset the flip flopand the power dmos will again conduct. this current protection method,ensuresa constantcurrent outputwhen the systemis overloadedor shortcircuited and limitsthe switching frequency, in this condition,to 40khz. the reset and power fail circuit (fig. 4), generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage di- vider. the reset signal, is generated with a delay time programmed by a externalcapacitor on the de- lay pin. when the supply voltage falls below the threshold or the output voltage goes below 5v, the resetoutput goes low immediately. the reset output is an open drain. fig. 4a shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5v. fig. 4b shows the case when the output is 5.1v, but the supply voltage is not yet higher than the fixed threshold. the thermal protection disables circuit operation when the junction temperature reaches about 150 c and has a hysterysis to prevent unstable conditions. circuit operation l4972a-L4972AD 4/23
figure 1 : feedforward waveform. figure 2 : soft start function. figure 3 : limiting current function. l4972a-L4972AD 5/23
figure 4 : reset and power fail functions. b a l4972a-L4972AD 6/23
electrical characteristics (refer to the test circuit, t j =25 c, v i = 35v, r 4 = 30k w , c 9 = 2.7nf, f sw = 100khztyp, unless otherwise specified) dynamic characteristics symbo l parameter t est co nd itions min. t yp. max. unit fig . v i input volt. range (pin 11) v o =v ref to 40v i o = 2a (**) 15 50 v 5 v o output voltage v i =15v to 50v i o = 1a; v o =v ref 5 5.1 5.2 v 5 d v o line regulation v i = 15v to 50v i o = 0.5a; v o =v ref 12 30 mv d v o load regulation v o =v ref i o = 0.5a to 2a 7 20 mv v d dropout voltage between pin 11 and 20 i o = 2a 0.25 0.4 v i 20l max limiting current v i = 15v to 50v v o =v ref to 40v 2.5 2.8 3.5 a h efficiency (*) i o = 2a, f = 100khz v o =v ref v o = 12v 75 85 90 % % svr supply voltage ripple rejection v i = 2vrms; i o =1a f = 100hz; v o =v ref 56 60 db 5 f switching frequency 90 100 110 khz 5 d f/ d vi voltage stability of switching frequency v i = 15v to 45v 2 6 % 5 d f/t j temperature stability of switching frequency t j = 0 to 125 c1%5 f max maximum operating switching frequency v o =v ref r 4 = 15k w i o =2ac 9 = 2.2nf 200 khz 5 (*) only for dip version (**) pulse testing with a low duty cycle v ref section (pin 13) symbol parameter test condition min. typ. max. unit fig. v 13 reference voltage 5 5.1 5.2 v 7 d v 13 line regulation v i = 15v to 50v 10 25 mv 7 d v 13 load regulation i 13 = 0 to 1ma 20 40 mv 7 d v 13 d t average temperature coefficient reference voltage t j =0 c to 125 c 0.4 mv/ c7 i 13 short short circuit current limit v 13 = 0 70 ma 7 v start section (pin 15) symbol parameter test condition min. typ. max. unit fig. v 14 reference voltage 11.4 12 12.6 v 7 d v 14 line regulation v i = 15 to 50v 0.6 1.4 v 7 d v 14 load regulation i 14 = 0 to 1ma 50 200 mv 7 i 14 short short circuit current limit v 15 =0v 80 ma 7 l4972a-L4972AD 7/23
electrical characteristics (continued) dc characteristics symbol parameter test condition min. typ. max. unit fig. v 11on turn-on threshold 10 11 12 v 7a v 11 hyst turn-off hysteresys 1 v 7a i 11q quiescent current v 8 =0; s1=d 13 19 ma 7a i 11oq operating supply current v 8 = 0; s1 = b; s2 = b 16 23 ma 7a i 20l out leak current v i = 55v; s3 = a; v 8 =0 2 ma 7a soft start (pin 8) symbol parameter test condition min. typ. max. unit fig. i 8 soft start source current v 8 = 3v; v 9 = 0v 80 115 150 m a7b v 8 output saturation voltage i 8 = 20ma; v 11 = 10v i 8 = 200 m a; v 11 = 10v 1 0.7 v v 7b 7b error amplifier symbol parameter test condition min. typ. max. unit fig. v 7h high level out voltage i 7 = 100 m a; s1 = c v 9 = 4.7v 6v7c v 7l low level out voltage i 7 = 100 m a; s1 = c v 9 = 5.3v; 1.2 v 7c i 7h source output current v 7 = 1v; v 7 = 4.7v 100 150 m a7c -i 7l sink output current v 7 = 6v; v 9 = 5.3v 100 150 m a7c i 9 input bias current s1 = b; r s = 10k w 0.4 3 m a7c g v dc open loop gain s1 = a; r s =10 w 60 db 7c svr supply voltage rejection 15 < v i < 50v 60 80 db 7c v os input offset voltage r s =50 w s1 = a 2 10 mv 7c ramp generator (pin 18) symbol parameter test condition min. typ. max. unit fig. v 18 ramp valley s1 = b; s2 = b 1.2 1.5 v 7a v 18 ramp peak s1 = b v i = 15v s2 = b v i = 45v 2.5 5.5 v v 7a 7a i 18 min. ramp current s1 = a; i 17 = 100 m a 270 300 m a7a i 18 max. ramp current s1 = a; i 17 = 1ma 2.4 2.7 ma 7a sync function (pin 10) symbol parameter test condition min. typ. max. unit fig. v 10 low input voltage v i = 15v to 50v; v 8 =0; s1 = b; s2 = b; s4 = b 0.3 0.9 v 7a v 10 high input voltage v8 = 0; s1 = b; s2 = b; s4 = b 2.5 5.5 v 7a i 10l sync input current with low input voltage v 10 =v 18 = 0.9v; s4 = b; s1 = b; s2 = b 0.4 ma 7a i 10h input current with high input voltage v 10 = 2.5v 1.5 ma 7a v 10 output amplitude 4 5 v t w output pulse width v thr = 2.5v 0.3 0.5 0.8 m s l4972a-L4972AD 8/23
reset and power fail functions symbo l parameter t est co nd itions min. t yp. max. unit fig . v 9r rising thereshold voltage (pin 9) v i = 15 to 50v v 4 = 5.3v v ref -130 v ref -100 v ref -80 v mv 7d v 9f falling thereshold voltage (pin 9) vi = 15 to 50v v 4 = 5.3v 4.77 vref -200 v ref -160 v mv 7d v 2h delay high threshold volt. vi = 15 to 50v v 4 = 5.3v v 9 =v 13 4.95 5.1 5.25 v 7d v 2l delay low threshold volt. vi = 15 to 50v v 4 = 4.7v v 9 =v 13 1 1.1 1.2 v 7d i 2so delay source current v 4 = 5.3v; v 2 =3v 306080 m a7d i 2si delay source sink current v 4 = 4.7v; v 2 =3v 10 ma 7d v 3s output saturation voltage i 3 = 15ma; s1 = b v 4 = 4.7v 0.4 v 7d i 3 output leak current v3 = 50v; s1 = a 100 m a7d v 4r rising threshold voltage v9 = v 13 4.95 5.1 5.25 v 7d v 4h hysteresis 0.4 0.5 0.6 v 7d i 4 input bias current 1 3 m a7d electrical characteristics (continued) f typical performances (using evaluation board) : n = 83% (v i = 35v ; v o = vref ; i o =2a;f sw = 100khz) v o ripple = 30mv (at 1a) line regulation = 12mv (v i = 15 to 50v) load regulation = 7mv (i o = 0.5 to 2a) for component values refer to the fig. 5 (part list). l4972a-L4972AD 9/23
part list r 1 = 30k w r 2 = 10k w r 3 = 15k w r 4 = 30k w r 5 =22 w r 6 = 4.7k w r 7 = see table a r 8 = option r 9 = 4.7k w *c 1 =c 2 = 1000 m f 63v eyf (roe) c 3 =c 4 =c 5 =c 6 = 2,2 m f 50v c 7 = 390pf film c 8 = 22nf mkt 1837 (ero) c 9 = 2.7nf kp 1830 (ero) c 10 = 0.33 m f film c 11 = 1nf ** c 12 =c 13 =c 14 = 100 m f 40v ekr (roe) c 15 =1 m f film d1 = sb 560 (or equivalent) l1 = 150 m h core 58310 magnetics 45 turns 0.91mm (awg 19) cogema 949181 * 2 capacitors in parallel to increase input rms current capability. * * 3 capacitors in parallel to reduce total output esr. note: in the test and application circuit for l4972d are not mounted c2, c14 and r8. table b suggested boostrap capacitors operating frequency boostrap cap.c10 f = 20khz 680nf f = 50khz 470nf f = 100khz 330nf f = 200khz 220nf f = 500khz 100nf figure 6a : component layout of fig.5 (1 : 1 scale). evaluation board available (only for dip version) table a v 0 r 9 r 7 12v 15v 18v 24v 4.7k w 4.7k w 4.7k w 4.7k w 6.2kw 9.1k w 12 w 18 w l4972a-L4972AD 10/23
figure 7 : dc test circuits. figure 6b: p.c. board and component layout of the circuit of fig. 5. (1:1 scale) l4972a-L4972AD 11/23
figure 7c. figure 7b. figure 7a. l4972a-L4972AD 12/23
figure 7d. figure 8 : quiescent drain current vs. supply voltage (0% duty cycle - see fig. 7a). figure 9 : quiescentdrain current vs. junction temperature (0% duty cycle). l4972a-L4972AD 13/23
figure 10 : quiescent drain current vs. duty cy- cle. figure 11 : reference voltage (pin 13) vs. vi (see fig. 7). figure 12 : reference voltage (pin 13) vs. junc- tion temperature (see fig. 7). figure 13 : referencevoltage (pin 14) vs. vi (see fig. 7). figure 14 : reference voltage (pin 14) vs. junc- tion temperature (see fig. 7). figure 15 : reference voltage 5.1v (pin 13) sup- ply voltage ripple rejection vs. fre- svr (db) l4972a-L4972AD 14/23
figure 16 : switching frequency vs. input voltage (see fig. 5). figure 17 : switching frequency vs. junction temperature (see fig. 5). figure 18 : switching frequency vs. r4 (see fig.5). figure 19 : maximum duty cycle vs. frequency. figure 20 : supply voltage ripple rejection vs. frequency (see fig. 5). figure 21 : efficiency vs. output voltage. l4972a-L4972AD 15/23
figure 22 : line transient response (see fig. 5). figure 23 : load transient response (see fig. 5). figure 24 : dropout voltage between pin 11 and pin 20 vs. current at pin 20. figure 25 : .dropout voltage between pin 11 and pin 20 vs. junction temperature. figure 26 : power dissipation (device only) vs. input voltage. figure 27 : power dissipation (device only) vs. input voltage. l4972a-L4972AD 16/23
figure 28 : power dissipation (device only) vs. output voltage. figure 29 : power dissipation (device only) vs. outputvoltage. figure 30 : power dissipation (device only) vs. output current. figure 31 : power dissipation (device only) vs. output current. figure 32 : efficiency vs. output current. figure 33 : test pcb thermal characteristic. l4972a-L4972AD 17/23
figure 34 : junction to ambientthermal resistance vs. area onboard heatsink (dip 16+2+2) figure 35: junction to ambient thermal resistance vs. area on board heatsink (so20) figure 36: maximum allowable power dissipa- tion vs. ambient temperature (pow- erdip) figure 37: maximum allowable power dissipa- tion vs. ambient temperature (so20) figure 38: open loop frequency and phase of er- ror amplifier (see fig. 7c). l4972a-L4972AD 18/23
figure 39 : 2a 5.1v low cost application circuit. figure 40 : a 5.1v/12vmultiple supply. note the synchronization between the l4972a and l4970a. l4972a-L4972AD 19/23
figure 41 : l4972a's sync. example. figure 42: 1a/24v multiple supply. note the synchronization between the l4972a and l4962 l4972a-L4972AD 20/23
dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.85 1.40 0.033 0.055 b 0.50 0.020 b1 0.38 0.50 0.015 0.020 d 24.80 0.976 e 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 f 7.10 0.280 i 5.10 0.201 l 3.30 0.130 z 1.27 0.050 powerdip 20 outline and mechanical data l4972a-L4972AD 21/23
11 0 11 20 a e b d e l k h a1 c so20mec hx45 so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k0 (min.)8 (max.) outline and mechanical data l4972a-L4972AD 22/23
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmi- croelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com l4972a-L4972AD 23/23

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